1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device with a test circuit, more particularly, to a gate array type large-scale integrated circuit (gate array LSI) having an improved test circuit.
2. Description of the Related Art
Recent research in the field of LSI testing has concentrated on the design of more effective test patterns using computer-aided-design (CAD) fault simulation and the design of more effective, simpler test circuits for incorporation in LSI's to allow testing by the scan pass method.
Testing by test patterns using CAD fault simulation, however, is disadvantageous in view of the long time required for the fault simulation program, which time is increasing in accordance with the increase in the scale of LSI's. Accordingly, testing by the incorporation of test circuits and the scan pass method is preferable. One of the better known scan pass methods now in use is the level sensitive scan design (LSSD) method of the IBM Corporation. Specifically, the logic circuit in the LSI is divided into combinational circuit portions and flip-flop circuit portions. The flip-flop circuits can be connected in series through switching circuits provided in those flip-flop circuits. When connected, the flip-flop circuits constitute a shift register. The test of the circuit is performed by switching between a "shift mode" and a "normal mode". In the shift mode, a scan signal is input to the shift register. In other words, data is applied to the shift register to set up the flip-flop circuits as a predetermined "1" or "0". The flip-flop circuits are then disconnected by the switching circuits and returned to the logic circuit. A predetermined logic operation is performed, and the flip-flop circuits then reconnected to form the shift register, after which the data of the shift register is read out and checked.
The above method has several problems; for example, the LSI must be designed to allow the formation of a shift register by the flip-flop circuits, and excessive signal lines must be provided to allow different types of LSI's to be checked. Also, since this method utilizes the logic circuit, the circuit test is dependent on the complexity of the LSI. This is because each gate state is set by the logic operation through external terminals of the LSI. Finally, this method requires a change in the design of the test circuit and the wiring thereof for each different type of LSI.
As one solution to the above problem, the following gate array LSI with a test circuit was proposed in Japanese Examined Patent Publication (Kokai) No. 61-42934 (corresponding to U.S. patent application Ser. No. 760,347). This prior art discloses a gate array LSI with a test circuit constituted by row selection wires provided along the gate cells in a row direction; column read-out wires provided along the gate cells in a column direction, row selection means for selecting any of the row selection wires and for selecting any of the gate cells connected to the selected row selection wire; column selection means for selecting and reading out the gate cells arranged in the logic circuit through the column read-out wire; and, switching means connected between the row selection wire and the output of the gate cell and being turned ON/OFF by the row selection means.
In this prior art, however, although it is possible to check the output of the gate cell using the switching means and row selection means, it is difficult to check an internal circuit of the gate cell because a test terminal is not provided at an input of the gate cell and the test is performed through the logic circuit. Accordingly, the test is dependent on the complexity of the logic circuit.